M2F1G64CB88A4N / M2F2G64CB8HA4N
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR3 SDRAM DIMM Preliminary
REV 0.1 9
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Serial Presence Detect -- Part 1 of 2 (2GB)
256Mx64 2 Ranks UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8, 8Banks, 8K Refresh, 1.5V DDR3 SDRAMs with SPD
Serial PD Data Entry
(Hexadecimal)
CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
Module type (form factor)
SDRAM Device density and banks
SDRAM device row and column count
Module ranks and device DQ count
ECC tag and module memory Bus width
Fine timebase dividend/divisor (in ps)
Minimum SDRAM cycle time (tCKmin) (ns)
Minimum CAS latency time (tAAmin) (ns)
Minimum write recovery time (tWRmin)
Minimum -to- delay (tRCDmin) (ns)
Minimum Row Active to Row Active delay (tRRDmin) (ns)
Minimum row Precharge delay (tRPmin) (ns)
Upper nibble for tRAS and tRC
Minimum Active-to-Precharge delay (tRASmin) (ns)
Minimum Active-to-Active/Refresh delay (tRCmin) (ns)
Minimum refresh recovery delay (tRFCmin) LSB
Minimum refresh recovery delay (tRFCmin) MSB
Minimum internal Write-to-Read command delay (tWTRmin)
Minimum internal Read-to-Precharge command delay
(tRTPmin)
Minimum four active window delay (tFAWmin) LSB
Minimum four active window delay (tFAWmin) MSB
SDRAM device output drivers suported
RZQ / 6,RZQ / 7,
DLL-Off Mode Support,
SDRAM device thermal and refresh options
Extended Temperature Range, ASR,
ODTS, PASR,
Non Thermal Sensor Support
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