Elixir M2F2G64CB8HA4N-CG Datasheet download pdf (Page 17)

M2F1G64CB88A4N / M2F2G64CB8HA4N

1GB: 128M x 64 / 2GB: 256M x 64

Unbuffered DDR3 SDRAM DIMM Preliminary

REV 0.1 17

06/2008

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specifications for DDR3 SDRAM Devices Used on Module

DDR3-1600

Parameter

Symbol

Min

Max

Units

Clock Timing

Minimum Clock Cycle time (DLL off mode)

tCK(DLL_OFF)

Average high pulse width

tCH(avg)

0.47

0.53

tCK(avg)

Average low pulse width

tCL(avg)

0.47

0.53

tCK(avg)

Absolute Clock Period

tCK(abs)

tCK(avg)min + tJIT(per)min

tCK(avg)max +tJIT(per)max

Absolute clock high pulse width

tCH(abs)

0.43

Absolute clock low pulse width

tCL(abs)

0.43

Clock Period Jitter

tJIT(per)

-70

Clock Period Jitter during DLL locking period

tJIT(per,lck)

-60

Cycle to Cycle Period Jitter

tJIT(cc)

140

Cycle to Cycle Period Jitter during DLL locking period

tJIT(cc,lck)

120

Duty Cycle Jitter

tJIT(duty)

Cumulative error across 2 cycles

tERR(2per)

-103

103

Cumulative error across 3 cycles

tERR(3per)

-122

122

Cumulative error across 4 cycles

tERR(4per)

-136

136

Cumulative error across 5 cycles

tERR(5per)

-147

147

Cumulative error across 6 cycles

tERR(6per)

-155

155

Cumulative error across 7 cycles

tERR(7per)

-163

163

Cumulative error across 8 cycles

tERR(8per)

-169

169

Cumulative error across 9 cycles

tERR(9per)

-175

175

Cumulative error across 10 cycles

tERR(10per)

-180

180

Cumulative error across n=11~50 cycles

tERR(nper)

tERR(npr)min =(1+

0.68In(n))*tJIT(per)min

tERR(npr)max =(1+

0.68In(n))*tJIT(per)max

Data Timing

DQS,  to DQ skew, per group, per access

tDQSQ

100

DQ output hold time from DQS, 

tQH

0.38

tCK(avg)

DQ low-impedance time from CK, 

tLZ(DQ)

-450

225

DQ high-impedance time from CK, 

tHZ(DQ)

225

Data setup time to DQS, DQS reference to Vih(ac) / Vil(ac) levels

tDS(base)

TBD

Data hold time to DQS, DQS reference to Vih(ac) / Vil(ac) levels

tDH(base)

TBD

Data Strobe Timing

DQS,  differential READ Preamble

tRPRE

0.9

tCK(avg)

DQS,  differential READ Postamble

tRPST

0.3

tCK(avg)

DQS,  differential output high time

tQSH

0.40

tCK(avg)

DQS,  differential output low time

tQSL

0.40

tCK(avg)

DQS,  differential WRITE Preamble

tWPRE

0.9

tCK(avg)

DQS,  differential WRITE Postamble

tWPST

0.3

tCK(avg)

DQS,  rising dege output access time from rising CK, 

tDQSCK

-225

225

DQS,  low-impedance time (Reference from RL-1)

tLZ(DQS)

-450

225

DQS,  high-impedance time (Reference from RL + BL/2)

tHZ(DQS)

225

DQS,  differential input low pulse width

tDQSL

0.4

0.6

tCK(avg)

DQS,  differential input high pulse width

tDQSH

0.4

0.6

tCK(avg)

DQS,  rising edge to CK,  rising edge

tDQSS

-0.25

0.25

tCK(avg)

DQS,  falling edge setup time to CK,  rising edge

tDSS

0.2

tCK(avg)

DQS,  falling edge hold time to CK,  rising edge

tDSH

0.2

tCK(avg)

1 2 ... 12 13 14 15 16 17 18 19 20 21 22

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Elixir M2F2G64CB8HA4N-CG Datasheet Page 17

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