Elixir M2F2G64CB8HA4N-CG Datasheet download pdf (Page 4)

M2F1G64CB88A4N / M2F2G64CB8HA4N

1GB: 128M x 64 / 2GB: 256M x 64

Unbuffered DDR3 SDRAM DIMM Preliminary

REV 0.1 4

06/2008

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol

Type

Polarity

Function

CK0-CK1

-

SSTL

Differential

crossing

CK and  are differential clock inputs. All the DDR3 SDRAM address/control inputs

are sampled on the crossing of positive edge of CK and negative edge of . Output

(read) data is reference to the crossing of CK and .

CKE0-CKE1

SSTL

Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh

mode.

-

SSTL

Active

Low

Enables the associated SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new

commands are ignored but previous operations continue. This signal provides for

external rank selection on systems with multiple ranks.

, , 

SSTL

Active

Low

, ,  (along with ) define the command being entered.

REFDQ

Supply

Reference voltage for SSTL15 I/O inputs

REFCA

Supply

Reference voltage for SSTL15 command/address inputs

DDQ

Supply

Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity.

ODT0-ODT1

SSTL

Active

High

When high, termination resistance is enabled for all DQ, DQS, , and DM pins,

assuming this function is enabled in the Mode Register 1 (MR1).

BA0 – BA2

SSTL

Selects which SDRAM bank is to be active.

A0 – A13

SSTL

During a Bank Activate command cycle, Address input defines the row address

(RA0-RA13).

During a Read or Write command cycle, Address input defines the column address. In

addition to the column address, AP is used to invoke autoprecharge operation at the

end of the burst read or write cycle. If AP is low, autoprecharge is disabled. During a

Precharge command cycle, AP is used in conjunction with B0 and B1 to control which

banks(s) to precharge. If AP is high, all banks will be precharged regardless of the state

of BA0, BA1, or BA2. If AP is low, BA0, BA1, and BA2 are used to define which bank to

precahrge. A12 () is sampled during READ and WRITE commands to determine if

burst chop (on-the –fly) will be performed (High, no burst chop; Low, burst chopped).

DQ0 – DQ63

SSTL

Active

High

Data and Check Bit Input/Output pins.

VDD, VSS

Supply

Power and ground for the DDR3 SDRAM input buffers and core logic.

DQS0 – DQS7

 – 

SSTL

Differential

crossing

Data strobe for input and output data.

DM0 – DM7

Input

Active

High

DM is an input mask signal for write data. Input data is masked when DM is sampled

High coincident with that input data during a write access. DM is sampled on both

edges of DQS. Although DM pins are input only, the DM loading matches the DQ and

DQS loadings.

SA0 – SA2

These signals are tied at the system planar to either Vss or V

DDSPD

to configure the

serial SPD EEPROM address range.

SDA

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A

external resistor must be connected from the SDA bus line to VDD to act as a pull-up on

the system board.

SCL

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

DDSPD

Supply

Power Supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power

plane. EEPROM supply is operable from 3.0V to 3.6V.

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Elixir M2F2G64CB8HA4N-CG Datasheet Page 4

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