Elixir M2X4G64CB8HG9N-DG Datasheet Page 11

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M2X2G64CB88G7(H)N / M2X4G64CB8HG5(9)N
2GB: 256M x 64 / 4GB: 512M x 64
PC3-12800
Unbuffered DDR3 SDRAM DIMM
REV 1.1 11
10/2011
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
tRTPmax.: -
Delay from start of internal write
transaction to internal read command
tWTR
tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.:
WRITE recovery time
tWR
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command period
tRC
CAS# to CAS# command delay
tCCD
4
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
nCK
ACTIVE to PRECHARGE command period
tRAS
Standard Speed Bins
ACTIVE to ACTIVE command period for 1KB page size
tRRD
tRRDmin.: max(4nCK, 6ns)
tRRDmax.:
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.:
Four activate window for 1KB page size
tFAW
30
-
ns
Four activate window for 2KB page size
tFAW
40
-
ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base)
45
-
ps
Command and Address hold time from CK, CK#
referenced to Vih(dc) / Vil(dc) levels
tIH(base)
120
-
ps
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base) AC150
170
-
ps
Control and Address Input pulse width for each input
tIPW
560
-
ps
Calibration Timing
Power-up and RESET calibration time
tZQinit
512
-
nCK
Normal operation Full calibration time
tZQoper
256
-
nCK
Normal operation Short calibration time
tZQCS
64
-
nCK
Reset Timing
Exit Reset from CKE HIGH to a valid command
tXPR
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a locked DLL
tXS
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
nCK
Minimum CKE low width for Self Refresh entry to exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tCKSRX
tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to commands
not requiring a locked DLL
tXP
tXPmin.: max(3nCK, 6ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width
tCKE
tCKEmin.: max(3nCK ,5ns)
tCKEmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
tCPDEDmin.: -
nCK
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down entry
tACTPDEN
tACTPDENmin.: 1
tACTPDENmax.: -
nCK
Timing of PRE or PREA command to Power Down entry
tPRPDEN
tPRPDENmin.: 1
tPRPDENmax.: -
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
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