M2F1G64CBH4B5(9)P / M2F2G64CB88B7(H)N / M2F4G64CB8HB5(9)N
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
REV 1.1 21
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Timing of RD/RDA command to Power Down entry
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
tWRPDENmax.: -
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
Timing of WR command to Power Down entry (BC4MRS)
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: -
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
Timing of REF command to Power Down entry
tREFPDENmin.: 1
tREFPDENmax.: -
Timing of MRS command to Power Down entry
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT high time without write command or
with write command and BC4
ODTH4min.: 4
ODTH4max.: -
ODT high time with Write command and BL8
ODTH8min.: 6
ODTH8max.: -
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
First DQS/DQS# rising edge after
write leveling mode is programmed
DQS/DQS# delay after write leveling mode is programmed
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
Write leveling hold time from rising DQS, DQS#
crossing to rising CK, CK# crossing
Write leveling output delay
Write leveling output error
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